As is well known, solid state storage devices such as SD cards or solid state drives (SSD) are widely used in various electronic devices.
FIG. 1 is a schematic functional block diagram illustrating a conventional solid state storage device. As shown in FIG. 1, the solid state storage device 10 comprises an interface controller 101 and a non-volatile memory 105. The non-volatile memory 105 further comprises a memory array 109 and an array control circuit 111.
The solid state storage device 10 is connected with a host 14 through an external bus 12. Generally, the external bus 12 is an USB bus, a SATA bus, a PCIe bus, or the like. Moreover, the interface controller 101 is connected with the non-volatile memory 105 through an internal bus 113. According to a write command from the host 14, the interface controller 101 controls the array control circuit 111 to store the write data from the host 14 to the non-volatile memory 105. Alternatively, according to a read command from the host 14, the interface controller 101 controls the array control circuit 111 to acquire a read data from the non-volatile memory 105. In addition, the read data is transmitted to the host 14 through the interface controller 101.
Generally, the memory array 109 comprises plural memory cells. Depending on the data amount to be stored in the memory cell, the memory cells may be classified into three types, i.e. a single-level cell (SLC), a multi-level cell (MLC) and a triple-level cell (TLC). The SLC can store only one bit of data per cell. The MLC can store two bits of data per cell. The TLC can store three bits of data per cell.
In the memory array 109, each memory cell comprises a floating gate transistor. By adjusting the number of hot carriers injected into a floating gate of the floating gate transistor, the array control circuit 111 controls the storing state of the floating gate transistor. In other words, the floating gate transistor of each SLC has two storing states, the floating gate transistor of each MLC has four storing states, and the floating gate transistor of each TLC has eight storing states.
Moreover, a threshold voltage (VTH) of the floating gate transistor is determined according to the amount of the hot carriers stored in the floating gate. If a floating gate transistor has a higher threshold voltage, it means that a higher gate voltage is required to turn on the floating gate transistor. Whereas, if a floating gate transistor has a lower threshold voltage, it means that the floating gate transistor can be turned on by a lower gate voltage.
During a program cycle of the solid state storage device, the interface controller 101 commands the array control circuit 111 to change the amount of the hot carriers to be injected into the floating gate. Consequently, the threshold voltage of the floating gate transistor is correspondingly changed. During a read cycle, the array control circuit 111 provides a read voltage to the floating gate transistor, and determines the storing state of the floating gate transistor by judging whether the floating gate transistor is turned on or not.
FIG. 2A schematically illustrates the threshold voltage distribution curves of triple-level cells in different storing states. According to the number of injected hot carriers, the triple-level cell has eight storing states which are marked as “000”˜“111”. Before the hot carriers are injected into the memory cell, the memory cell is in a storing state “000”. That is, after an erase cycle, the memory cell is restored to the storing state “000”, and no hot carriers are retained in the memory cell. During a program cycle, as the number of the injected hot carriers increases, the memory cell is sequentially drifting in the other seven storing states.
In practice, even if many memory cells are in the same storing state during the program cycle, the threshold voltages of these cells are not all identical. That is, the threshold voltages of these memory cells are distributed in a specified distribution curve with a median threshold voltage. The median threshold voltage of the memory cells in the storing state “000” is 0V. The median threshold voltage of the memory cells in the storing state “001” is 5V. The median threshold voltage of the memory cells in the storing state “010” is 10V. The median threshold voltage of the memory cells in the storing state “011” is 15V. The median threshold voltage of the memory cells in the storing state “100” is 20V. The median threshold voltage of the memory cells in the storing state “101” is 25V. The median threshold voltage of the memory cells in the storing state “110” is 30V. The median threshold voltage of the memory cells in the storing state “111” is 35V. That is to say, the median threshold voltage for a greater number of memory cells in the storing state “001” is 5V.
Please refer to FIG. 2A again. According to the above characteristics of the triple-level cell, a read voltage set including seven read voltages Vra˜Vrg is defined. During the read cycle, the array control circuit 111 provides, in a pre-defined order, the seven read voltages of the read voltage set to a word line (not shown) in order to detect the storing states of the triple-level cells.
For example, when the read voltage Vrd is provided to the memory array 109, a most significant bit (MSB) of the memory cell can be determined. If the threshold voltage of the memory cell is lower than the read voltage Vrd and the memory cell can be turned, the array control circuit 111 judges that the MSB of the memory cell is “0”. Whereas, if the threshold voltage of the memory cell is higher than the read voltage Vrd and the memory cell cannot be turned, the array controlling circuit 111 judges that the MSB of the memory cell is “1”.
Moreover, after the array control circuit 111 judges that the MSB of the memory cell is “0”, the array control circuit 111 further provides the read voltages Vra, Vrb, and Vrc in a pre-defined order to judge the other two bits of the memory cell. Similarly, after the array control circuit 111 judges that the MSB of the memory cell is “1”, the array control circuit 111 further provides the read voltages Vre, Vrf, and Vrg in a pre-defined order to judge the other two bits of the memory cell. In other words, the storing state of the triple-level cell is determined according to the read voltages Vra˜Vrg.
Moreover, the memory array 109 of the non-volatile memory 105 is divided into plural blocks. The array control circuit 111 reads the triple-level cells of the blocks according to the corresponding read voltage sets. For example, in case that the memory array 109 contains 1024 blocks, the interface controller 101 may record 1024 read voltage sets corresponding to the 1024 blocks and reads to corresponding blocks through the array control circuit 111.
However, after the non-volatile memory 105 has been used for a certain period of time, the characteristics of the triple-level cells are subjected to changes. That is, the hot carriers are gradually ejected from the floating gate of the triple-level cell with the increasing of time. Under this circumstance, the threshold voltage distribution curves of the storing states of all memory cells in the non-volatile memory 105 are possibly changed, and the median threshold voltages are shifted. For solving this drawback, during an idle period, the interface controller 101 performs a background monitoring operation on a first block to monitor the changes of the read voltage sets of the corresponding blocks and modifies the read voltage sets if necessary. The term “idle period” indicates that electric power is supplied to the solid state storage device 10 but no data are transmitted between the solid state storage device 10 and the host 14.
FIG. 2B schematically illustrates the shift of the threshold voltage distribution curves of triple-level cells in different storing states. After the solid state storage device 10 has been powered off for a long enough time, the threshold voltage distribution curves of triple-level cells are possibly shifted. The interface controller 101 cannot perform the background monitoring operation when the solid state storage device 10 is powered off. Once the solid state storage device 10 is powered on again, the interface controller 101 commands the array control circuit 111 to read the data of a corresponding block according to the read voltage set including the previous read voltages Vra˜Vrg. Since the previous read voltage set is not suitable for this threshold-voltage-shifted block, a great number of error-read bits are generated and thus the read data fail to be error corrected.
For accurately acquiring the read data, the interface controller 101 performs a red retry process to acquire accurate read voltage set. During the read retry process, the interface controller 101 selects one read voltage set of plural read voltage sets (e.g., M read voltage sets) from a retry table. Moreover, the array control circuit 111 reads the triple-level cells of a block according to the updated read voltage set.
If the data is not successfully read according to the selected read voltage set, the interface controller 101 selects another read voltage set of plural read voltage sets from the retry table, and the array control circuit 111 reads the triple-level cells of the block according to the updated read voltage set again. The above procedure is repeatedly done until the triple-level cells of the block are successively read according to a specified read voltage set including the read voltages Vra′˜Vrg′. In the worst situation, the interface controller 101 has to perform the read retry process for M times in order to accurately acquire the read voltage set.
For example, the memory array 109 of the non-volatile memory 105 contains 1024 blocks. For accurately acquiring the read voltage sets corresponding to the 1024 blocks, the interface controller 101 performs the read retry process for 1024×M times in the worst situation. Moreover, if the data is not successfully read according to the M read voltage sets of the retry table, it is necessary to use a special algorithm to find out the suitable read voltage set. Under this circumstance, it takes longer time to acquire the data.
As mentioned above, after the solid state storage device 10 has been powered off for a certain period of time, the threshold voltage distribution curves of triple-level cells are possibly shifted. Since the interface controller 101 has to consume much resource to perform the read retry process, the access speed of the solid state storage device 10 is largely reduced. In the worst situation, the access speed is about 5%˜10% of the optimal access speed.